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A Digital Physical Design Engineer with extensive experience working within the Semiconductor Industry will bring expert knowledge of STA and Timing Constraints to contribute to the high volume silicon production of a dynamic Semiconductor company. A top salary, Hybrid working and Shares will be offered. 

The Physical Design Engineer will ideally bring:

• A good Bachelors or Masters Degree in an Electronics subject.
• Proven experience of working within the Semiconductor industry.
• A good understanding of RTL to GDS implementation flow.
• Good Scripting capabilities.
• Expertise in Timing / SDC Constraints generation.
• Experience of modern semiconductor process technologies.
• Use of EDA tools.

The Role will involve:

• Working closely with the Architecture and RTL team to ensure right first time high-volume silicon production.
• Timing Constraints development.
• Timing analysis and full chip and block level timing closure.
• Block and chip level STA.
• Participating in developing improvements to scripts, flows and methodologies.
• Supporting IP and chip level integration.

If you are seeking a career move offering challenging work, a great salary package and the opportunity to contribute to tomorrows technology with a growing Company – apply now for full details.